library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mux_2to1 is
    Port ( X0 : in  STD_LOGIC_VECTOR(7 downto 0); --Вход 1
           X1 : in  STD_LOGIC_VECTOR(7 downto 0); --Вход 2
           C : in  STD_LOGIC; -- управление
           D : out  STD_LOGIC_VECTOR(7 downto 0)); --Выход
end mux_2to1;

architecture BEH of mux_2to1 is
begin
    process(C, X0, X1)
    begin
        if C = '0' then
            D <= X0;
        else
            D <= X1;
        end if;
    end process;
end BEH;